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www.irf.com 1 irs2608d spbf half-bridge driver packages description the irs2608d(s) is a high voltage, high speed power mosfet an igbt driver with dependent high and low side referenced output channels. proprietary hvic and la tch immune cmos technologies enable ruggedized mono lithic construction. the logic input is compatible with st andard cmos or lsttl output, down to 3.3 v logic. t he output drivers feature a high pulse current buffer stage d esigned for minimum driver crossconduction. the fl oating channel can be used to drive an nchannel power mosfet or 1 gbt in the high side configuration which operates u p to 600 v. features ? floating channel designed for bootstrap operation fully operational to +600 v tolerant to negative transient voltage C dv /dt immune ? gate drive supply range from 10 v to 20 v ? undervoltage lockout for both channels ? 3.3 v, 5 v and 15 v input logic compatible ? crossconduction prevention logic ? matched propagation delay for both channels ? high side output in phase with hin input ? low side output out of phase with lin input ? internal 530 ns deadtime ? lower di/dt gate driver for better noise immunity ? integrated bootstrap diode ? suitable for both trapezoidal and sinusoidal motor control ? rohs compliant june 1, 2011 irs2608dspbf 8-lead soic typical connection applications: * air conditioner *micro/mini inverter drives *general purpose inverters *motor control
www.irf.com 2 irs2608d spbf qualification information ? industrial ?? qualification level comments: this ic has passed jedecs industrial qualification. irs consumer qualification level is granted by extension of the higher industrial level. moisture sensitivity level msl2, 260 c (per ipc/jedec jstd020) human body model class 2 (per jedec standard jesd22a114) esd machine model class b (per eia/jedec standard eia/jesd22a115) ic latch-up test class i, level a (per jesd78) rohs compliant yes ? qualification standards can be found at internation al rectifiers web site http://www.irf.com/ ?? higher qualification ratings may be available shoul d the user have such requi rements. please contact your international rectifier sales r epresentative for further information.
www.irf.com 3 irs2608dspbf absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all vo ltage parameters are absolute voltages referenced to com. the thermal resistance and power dissipation ratin gs are measured under board mounted and still air conditions. recommended operating conditions for proper operation the device should be used with in the recommended conditions. the v s and com offset rating are tested with all supplies biased at 15v differential . symbol definition min. max. units v b high side floating supply absolute voltage v s +10 v s +20 v s static high side floating supply offset voltage co m 8(note 1) 600 v st transient high side floating supply offset voltage 50 (note2) 600 v ho high side floating output voltage v s v b v cc low side and logic fixed supply voltage 10 20 v lo low side output voltage 0 v cc v in logic input voltage com v cc v t a ambient temperature 40 125 c note 1: logic operational for v s of 8 v to +600 v. logic state held for v s of 8 v to C v bs. note 2: operational for transient negative vs of com 50 v with a 50 ns pulse width. guaranteed by design. r efer to the application information section of this datasheet f or more details. symbol definition min. max. units v b high side floating absolute voltage 0.3 620 v s high side floating supply offset voltage v b 20 v b + 0.3 v ho high side floating output voltage v s 0.3 v b + 0.3 v cc low side and logic fixed supply voltage 0.3 20 v lo low side output voltage 0.3 v cc + 0.3 v in logic input voltage (hin &lin) com 0.3 v cc + 0.3 com logic ground v cc 20 v cc + 0.3 v dv s /dt allowable offset supply voltage transient 50 v/ns p d package power dissipation @ ta +25c 0.625 w rth ja thermal resistance, junction to ambient 200 c/w t j junction temperature 150 t s storage temperature 50 150 t l lead temperature (soldering, 10 seconds) 300 c
www.irf.com 4 irs2608dspbf dynamic electrical characteristics v bias (v cc , v bs ) = 15 v, com = v cc , c l = 1000 pf, t a = 25c. symbol definition min typ max units test conditions t on turnon propagation delay 120 250 380 v s = 0 v or 600 v t off turnoff propagation delay 120 250 380 v s = 0 v or 600 v mt delay matching t on t off 60 t r turnon rise time 150 220 v s = 0 v t f turnoff fall time 50 80 v s = 0 v dt deadtime: lo turnoff to ho turnon(dt lo ho) & ho turnoff to lo turnon (dt holo) 350 530 800 mt delay matching time (t on , t off ) 60 mdt deadtime matching = dt loho dt holo 60 nsec v in = 0 v & 5 v without external deadtime static electrical characteristics v bias (v cc , v bs ) = 15v, and t a = 25c unless otherwise specified. the v il, v ih and i in parameters are referenced to com and are applicable to the respective input leads: h in and lin. the v o, i o and ron parameters are referenced to com and are applicable to the respective output leads: ho a nd lo. symbol definition min typ max units test conditions v ih logic 1 input voltage for hin & logic 0 for lin 2.2 v il logic 0 input voltage for hin & logic 1 for lin 0.8 v oh high level output voltage, v bias v o 0.8 1.4 v ol low level output voltage, v o 0.3 0.6 v i o = 20 ma i lk offset supply leakage current 50 v b = v s = 600 v i qbs quiescent v bs supply current 45 70 v in = 0 v or 4 v i qcc quiescent v cc supply current 1000 1700 3000 v in = 0 v or 4 v i in+ logic 1 input bias current 15 30 v in = 4 v i in logic 0 input bias current 10 20 a v in = 0 v v ccuv+ v bsuv+ v cc and v bs supply undervoltage positive going threshold 8.0 8.9 9.8 v ccuv v bsuv v cc and v bs supply undervoltage negative going threshold 7.4 8.2 9.0 v ccuvh v bsuvh hysteresis 0.7 v i o+ output high short circuit pulsed current 120 200 v o = 0 v, pw 10 us i o output low short circuit pulsed current 250 350 ma v o = 15 v, pw 10 us rbs bootstrap resistance 200 ohm
www.irf.com 5 irs2608dspbf functional block diagrams
www.irf.com 6 irs2608dspbf lead definitions symbol description hin logic input for high side gate driver output (ho), in phase lin logic input for low side driver output (lo), out of phase v b high side floating supply ho high side gate drive output v s high side floating supply return v cc low side and logic fixed supply lo low side gate drive output com low side return lead assignments irs 2608ds 8 lead soic 8 7 6 5 v cc v b hin 1 2 3 4 v s ho lo lin com
www.irf.com 7 irs2608dspbf application information and additional details informations regarding the following topics are inc luded as subsections within this section of the dat asheet. ? igbt/mosfet gate drive ? switching and timing relationships ? deadtime ? matched propagation delays ? input logic compatibility ? undervoltage lockout protection ? shootthrough protection ? integrated bootstrap functionality ? negative v s transient soa ? pcb layout tips ? integrated bootstrap fet limitation ? additional documentation igbt/mosfet gate drive the irs2608d hvics are designed to drive mosfet or igbt power devices. figures 1 and 2 illustrate sev eral parameters associated with the gate drive functiona lity of the hvic. the output current of the hvic, used to drive the gate of the power switch, is defined as i o . the voltage that drives the gate of the external power switch is defined as v ho for the highside power switch and v lo for the lowside power switch; this parameter is s ometimes generically called v out and in this case does not differentiate between th e highside or lowside output voltage. v s (or com) ho (or lo) v b (or v cc ) i o+ v ho (or v lo ) + v s (or com) ho (or lo) v b (or v cc ) i o figure 1: hvic sourcing current figure 2: hvic sinking current
www.irf.com 8 irs2608dspbf switching and timing relationships the relationships between the input and output sign als of the irs2608d are illustrated below in figure s 3, 4. from these figures, we can see the definitions of severa l timing parameters (i.e., pw in , pw out , t on , t off , t r , and t f ) associated with this device. 50% 10% 90% t r lin lo 90% 10% 50% t f t on t off figure 3: switching time waveforms figure 4: input/output timing diagram deadtime this family of hvics features integrated deadtime p rotection circuitry. the deadtime for these ics is fixed; other ics within irs hvic portfolio feature programmable deadtime for greater design flexibility. the deadtime feature inserts a time period (a minimum deadtime) in which both the high and lowside powe r switches are held off; this is done to ensure tha t the power switch being turned off has fully turned off before the second power sw itch is turned on. this minimum deadtime is automa tically inserter whenever the external deadtime is shorter than dt; external dead times larger than dt are not modified by the gate d river. figure 5 illustrates the deadtime period and the relationship between the ou tput gate signals. the deadtime circuitry of the irs2608d is matched w ith respect to the high and lowside outputs. fig ure 5 defines the two deadtime parameters (i.e., dt loho and dt holo ); the deadtime matching parameter (mdt) associated with the irs2608d specifies the maximum difference between dt loho and dt holo . matched propagation delays the irs2608d family of hvics is designed with propa gation delay matching circuitry. with this feature , the ics response at the output to a signal at the input req uires approximately the same time duration (i.e., t on , t off ) for both the lowside channels and the highside channels; the m aximum difference is specified by the delay matchin g parameter (mt). the propagation turnon delay (t on ) of the irs2608d is matched to the propagation tur non delay (t off ).
www.irf.com 9 irs2608dspbf figure 5: delay matching waveform definition input logic compatibility the inputs of this ic are compatible with standard cmos and ttl outputs. the irs2608d has been design ed to be compatible with 3.3 v and 5 v logiclevel signals. the irs2608d features an integrated 5.2 v zener cla mp on the /lin. f igure 6 illustrates an input signal to the irs2608d , its input threshold values, and the logic state o f the ic as a result of the input signal. input logic level lin input signal input signal (irs23364d) v ih v il input logic level high low low figure 6: hin & lin input thresholds
www.irf.com 10 irs2608dspbf undervoltage lockout protection this family of ics provides undervoltage lockout pr otection on both the v cc (logic and lowside circuitry) power supply and the v bs (highside circuitry) power supply. figure 7 is u sed to illustrate this concept; v cc (or v bs ) is plotted over time and as the waveform crosses the uvlo threshold (v ccuv+/ or v bsuv+/ ) the undervoltage protection is enabled or disabled. upon powerup, should the v cc voltage fail to reach the v ccuv+ threshold, the ic will not turnon. additionally, if the v cc voltage decreases below the v ccuv threshold during operation, the undervoltage locko ut circuitry will recognize a fault condition and shutdown the high and lowside gate drive outputs, and the fault pin will transition to the low state to inform the controller of the fault condition. upon powerup, should the v bs voltage fail to reach the v bsuv threshold, the ic will not turnon. additionally, if the v bs voltage decreases below the v bsuv threshold during operation, the undervoltage locko ut circuitry will recognize a fault condition, and shutdown the highside gate drive ou tputs of the ic. the uvlo protection ensures that the ic drives the external power devices only when the gate supply vo ltage is sufficient to fully enhance the power devices. wit hout this feature, the gates of the external power switch could be driven with a low voltage, resulting in the power s witch conducting current while the channel impedanc e is high; this could result in very high conduction losses within the power device and could lead to power device fai lure. figure 7: uvlo protection shoot-through protection the irs2608d highvoltage ics is equipped with shoo tthrough protection circuitry (also known as cross conduction prevention circuitry).
www.irf.com 11 irs2608dspbf integrated bootstrap functionality the irs2608d embeds an integrated bootstrap fet tha t allows an alternative drive of the bootstrap supp ly for a wide range of applications. a bootstrap fet is connected between the floating s upply v b and v cc (see fig. 8). figure 8: semplified bootfet connection the bootstrap fet is suitable for most pwm modulati on schemes, including trapezoidal control, and can be used either in parallel with the external bootstrap netw ork (diode+ resistor) or as a replacement of it. th e use of the integrated bootstrap as a replacement of the extern al bootstrap network may have some limitations in t he following situations: ? when the motor runs at a very low current (so that the negative phase voltage decay can be longer tha n 20us) and complementary pwm is not used. ? at a very high pwm duty cycle due to the bootstrap fet equivalent resistance (r bs , see page 3). the summary for the bootstrap state follows: ? bootstrap turns-off (immediately) or stays off when at least one of the following conditions are met : 1 ho goes/is high 2 v b goes/is high (> 1.1*v cc ) ? bootstrap turns-on when : 1 lo is high (low side is on) and v b is low (< 1.1(v cc )) 2 lo and ho are low after a lin transition from h to l (hb output is in tristate) and v b goes low (<1.1*v cc ) before a fixed time of 20us. 3 lo and ho are low after a hin transition from h to l (hb output is in tristate) and v b goes low (<1.1(v cc )) before a retriggerable time of 20us. in this cas e the time counter is kept in reset state until vb goes high (>1.1v cc ). please refer to the bootfet timing diagram for m ore details. vcc vb bootfet
www.irf.com 12 irs2608dspbf + vb 1.1*vcc hin lin bootstrap fet 20 us timer counter timer is reset timer is reset timer expired figure 9: bootfet timing diagram
www.irf.com 13 irs2608dspbf negative v s transient soa a common problem in todays highpower switching co nverters is the transient response of the switch no des voltage as the power switches transition on and off quickly wh ile carrying a large current. a typical 3phase in verter circuit is shown in figure 10; here we define the power switch es and diodes of the inverter. if the highside switch (e.g., the igbt q1 in figur es 11 and 12) switches off, while the u phase curre nt is flowing to an inductive load, a current commutation occurs from h ighside switch (q1) to the diode (d2) in parallel with the lowside switch of the same inverter leg. at the same insta nce, the voltage node v s1 , swings from the positive dc bus voltage to the negative dc bus voltage. figure 10: three phase inverter q1 on d2 v s1 q2 off i u dc+ bus dc bus figure 11: q1 conducting figure 12: d2 conducting also when the v phase current flows from the induct ive load back to the inverter (see figures 13 and 1 4), and q4 igbt switches on, the current commutation occurs from d3 to q4. at the same instance, the voltage node, v s2 , swings from the positive dc bus voltage to the negative dc bus voltage.
www.irf.com 14 irs2608dspbf figure 13: d3 conducting figure 14: q4 conducting however, in a real inverter circuit, the v s voltage swing does not stop at the level of the ne gative dc bus, rather it swings below the level of the negative dc bus. this undershoot voltage is called negative v s transient. the circuit shown in figure 15 depicts one leg of t he three phase inverter; figures 16 and 17 show a s implified illustration of the commutation of the current betw een q1 and d2. the parasitic inductances in the pow er circuit from the die bonding to the pcb tracks are lumped together i n l c and l e for each igbt. when the highside switch is on, v s1 is below the dc+ voltage by the voltage drops associat ed with the power switch and the parasitic elements of the circuit. when the highside power switch turns off, the load current momentarily flows in the lowside freewhee ling diode due to the inductive load connected to v s1 (the load is not shown in these figures). this cu rrent flows from the dc bus (which is connected to the com pin of the hvic) to the loa d and a negative voltage between v s1 and the dc bus is induced (i.e., the com pin of the hvic is at a higher poten tial than the v s pin). figure 15: parasitic elements figure 16: v s positive figure 17: v s negative in a typical motor drive system, dv/dt is typically designed to be in the range of 35 v/ns. the negat ive v s transient voltage can exceed this range during some events su ch as short circuit and overcurrent shutdown, when di/dt is greater than in normal operation. international rectifiers hvics have been designed for the robustness required in many of todays dema nding applications. an indication of the irs2608ds robus tness can be seen in figure 18, where there is repr esented the irs2608d safe operating area at v bs =15v based on repetitive negative v s spikes. a negative v s transient voltage falling in the grey area (outside soa) may lead to ic permanent damage; viceversa unwanted functional anomalies or permanent damage to the ic do not appear if negativ e vs transients fall inside soa. at v bs =15v in case of v s transients greater than 16.5 v for a period of ti me greater than 50 ns; the hvic will hold by design the highside outputs in the off state for 4 .5 s.
www.irf.com 15 irs2608dspbf figure 18: negative v s transient soa for irs2608d @ vbs=15v even though the irs2608d has been shown able to han dle these large negative v s transient conditions, it is highly recommended that the circuit designer always limit the negative v s transients as much as possible by careful pcb layout and component use. pcb layout tips distance between high and low voltage components: its strongly recommended to place the components tied to the floating voltage pins (v b and v s ) near the respective high voltage portions of the device. please see the case outline information in this datasheet for the details. ground plane: in order to minimize noise coupling, the ground pl ane should not be placed under or near the high voltage floating side. gate drive loops: current loops behave like antennas and are able to receive and transmit em noise (see figure 19). in order to reduce the em coupling and improve the power switch turn on/off performance, the gate driv e loops must be reduced as much as possible. moreover, current can be injected inside the gate drive loop via the igbt collectortogate parasitic capacitance. the parasitic autoinductanc e of the gate loop contributes to developing a volt age across the gateemitter, thus increasing the possibility of a self turnon effect.
www.irf.com 16 irs2608dspbf figure 19: antenna loops supply capacitor: it is recommended to place a bypass capacitor (c in ) between the v cc and com pins. a ceramic 1 f ceramic capacitor is suitable for most applications . this component should be placed as close as poss ible to the pins in order to reduce parasitic elements. routing and placement: power stage pcb parasitic elements can contribute to large negative voltage transients at the switch node; it is recommended to limit the phase v oltage negative transients. in order to avoid such conditions, it is recommended to 1) minimize the highside emitter to lowside collector distance, and 2) minimize the l owside emitter to negative bus rail stray inductance. however, where negative v s spikes remain excessive, further steps may be take n to reduce the spike. this includes placing a resistor (5 or less) between the v s pin and the switch node (see figure 20), and in some cases using a clamping diode between co m and v s (see figure 21). see dt044 at www.irf.com for more detailed information. figure 20: v s resistor figure 21: v s clamping diode integrated bootstrap fet limitation the integrated bootstrap fet functionality has an o perational limitation under the following bias cond itions applied to the hvic: ? vcc pin voltage = 0v and ? vs or vb pin voltage > 0 in the absence of a vcc bias, the integrated bootst rap fet voltage blocking capability is compromised and a current conduction path is created between vcc & vb pins, as illustrated in fig.22 below, resulting in power loss and possible damage to the hvic.
www.irf.com 17 irs2608dspbf figure 22: current conduction path between vcc and vb pin relevant application situations: the above mentioned bias condition may be encounter ed under the following situations: ? in a motor control application, a permanent magnet motor naturally rotating while vcc power is off. i n this condition, back emf is generated at a motor te rminal which causes high voltage bias on vs nodes resulting unwanted current flow to vcc. ? potential situations in other applications where v s/vb node voltage potential increases before the vc c voltage is available (for example due to sequencing delays in smps supplying vcc bias) application workaround: insertion of a standard pn junction diode between vcc pin of ic and positive terminal of vcc capacito rs (as illustrated in fig.23) prevents current conduction outof vcc pin of gate driver ic. it is important not to connect the vcc capacitor directly to pin of ic. diode selectio n is based on 25v rating or above & current capabil ity aligned to icc consumption of ic 100ma should cover most app lication situations. as an example, part number # l l4154 from diodes inc (25v/150ma standard diode) can be u sed. figure 23: diode insertion between vcc pin and vcc capacitor note that the forward voltage drop on the diode (vf ) must be taken into account when biasing the vcc p in of the ic to meet uvlo requirements. vcc pin bias = vcc suppl y voltage C vf of diode. vcc vss (or com) vb vcc capacitor vcc vss (or com) vb vcc capacitor
www.irf.com 18 irs2608dspbf additional documentation several technical documents related to the use of h vics are available at www.irf.com ; use the site search function and the document number to quickly locate them. be low is a short list of some of these documents. dt973: managing transients in control ic driven po wer stages an1123: bootstrap network analysis: focusing on th e integrated bootstrap functionality dt044: using monolithic high voltage gate drivers an978: hv floating mosgate driver ics
www.irf.com 19 irs2608dspbf parameters trend in temperature figures 2443 provide information on the experiment al performance of the irs2608d(s) hvic. the line p lotted in each figure is generated from actual lab data. a large n umber of individual samples from multiple wafer lot s were tested at three temperatures (40 oc, 25 oc, and 125 oc) in order t o generate the experimental (exp.) curve. the line labeled exp. consist of three data points (one data point at each of the tested temperatures) that have been connected toge ther to illustrate the understood trend. the individual data points on th e curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). fig. 24 turnon propagation delay vs. temperature fig. 25. turnoff propagation delay vs. temperature fig. 26. turnon rise time vs. temperature fig. 27. turnoff rise time vs. temperature 0 100 200 300 400 500 50 25 0 25 50 75 100 125 temperature ( o c) turnon propagation delay (ns) exp. 0 100 200 300 400 500 50 25 0 25 50 75 100 125 temperature ( o c) turnoff propagation delay (ns) exp. 0 50 100 150 200 250 50 25 0 25 50 75 100 125 temperature ( o c) turnon rise time (ns) exp. 0 25 50 75 100 125 50 25 0 25 50 75 100 125 temperature ( o c) turnoff fall time (ns) exp.
www.irf.com 20 irs2608dspbf fig. 28. v cc supply uv hysteresis vs. temperature fig. 29. v bs supply uv hysteresis vs. temperature fig. 30. v cc quiescent supply current vs. temperature fig. 31 v bs quiescent supply current vs. temperature fig. 32. v ccuv+ threshold vs. temperature fig. 33. v ccuv threshold vs. temperature 0 1 2 3 4 50 25 0 25 50 75 100 125 temperature ( o c) v ccuv hysteresis (v) exp. 0 1 2 3 4 50 25 0 25 50 75 100 125 temperature ( o c) v bsuv hysteresis (v) exp. 0 2 4 6 8 10 50 25 0 25 50 75 100 125 temperature ( o c) v cc quiescent current (ma) exp. 0 20 40 60 80 100 50 25 0 25 50 75 100 125 temperature ( o c) v bs quiescent current (a) exp. 0 3 6 9 12 50 25 0 25 50 75 100 125 temperature ( o c) v ccuv+ threshold (v) exp. 0 3 6 9 12 50 25 0 25 50 75 100 125 temperature ( o c) v ccuv threshold (v) exp.
www.irf.com 21 irs2608dspbf fig. 35 v bsuv threshold vs. temperature fig. 39. lin v th+ vs. temperature fig. 34. v bsuv+ threshold vs. temperature fig. 38. bootstrap resistance vs. temperature fig. 36. low level output voltage vs. temperature fig. 37. high level output voltage vs. temperature 0 3 6 9 12 50 25 0 25 50 75 100 125 temperature ( o c) v bsuv+ threshold (v) exp. 0 3 6 9 12 50 25 0 25 50 75 100 125 temperature ( o c) v bsuv threshold (v) exp. 0 100 200 300 400 50 25 0 25 50 75 100 125 temperature ( o c) low level output voltage (mv) exp. 0 100 200 300 400 50 25 0 25 50 75 100 125 temperature ( o c) high level output voltage (mv) exp. 0 100 200 300 400 500 50 25 0 25 50 75 100 125 temperature ( o c) bootstrap resistance () exp. 0 2 4 6 8 50 25 0 25 50 75 100 125 temperature ( o c) lin v th+ (v) exp.
www.irf.com 22 irs2608dspbf fig. 40. lin v th vs. temperature 0 2 4 6 8 50 25 0 25 50 75 100 125 temperature ( o c) lin vth (v) exp. 0 2 4 6 8 50 25 0 25 50 75 100 125 temperature ( o c) hin v th+ (v) exp. fig. 41. hin v th+ vs. temperature 0 2 4 6 8 50 25 0 25 50 75 100 125 temperature ( o c) hin v th (v) exp. fig. 42. hin v th vs. temperature 0 100 200 300 400 500 600 50 25 0 25 50 75 100 125 temperature ( o c) tbson_vcctyp(ns) exp. fig. 43. tbson_v cc typ vs. temperature
www.irf.com 23 irs2608dspbf case outlines
www.irf.com 24 irs2608dspbf tape and reel details: 8l-soic e f a c d g a b h note : controlling dim ension in m m loaded tape feed direction a h f e g d b c carrier tape dimension for 8soicn code min max min max a 7.90 8.10 0.311 0.318 b 3.90 4.10 0.153 0.161 c 11.70 12.30 0.46 0.484 d 5.45 5.55 0.214 0.218 e 6.30 6.50 0.248 0.255 f 5.10 5.30 0.200 0.208 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 8soicn code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 18.40 n/a 0.724 g 14.50 17.10 0.570 0.673 h 12.40 14.40 0.488 0.566 metric imperial
www.irf.com 25 irs2608dspbf the information provided in this document is believ ed to be accurate and reliable. however, internatio nal rectifier assumes no responsibility for the consequences of the use of this information . international rectifier assumes no responsibilit y for any infringement of patents or of other rights of third parties which may result from the u se of this information. no license is granted by i mplication or otherwise under any patent or patent rights of international rectifier. the spec ifications mentioned in this document are subject t o change without notice. this document supersedes and replaces all information previously supplied. for technical support, please contact irs technica l assistance center http://www.irf.com/technicalinfo/ world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 2527105 order information 8lead soic irs2608dspbf 8lead soic tape & reel irs2608dstrpbf
www.irf.com 26 irs2608dspbf revision history revision date comments/changed items 1.5 03-17-08 added application note to include nega tive vs curve 1.6 03-17-08 added qualification information on pa ge 2, disclaimer information on page 25, and updated information on pages 21-23 1.7 03-21-08 removed revision letter from jedec sta ndards under qualification information table. 1.8 04-18-08 removed available in lead-free from front page, replaced with rohs compliant, changed latch up level to a, changed bo otstrap turn-on at point 3 from lin to hin, added mt parameter into datasheet. 1.9 05-08-08 added suitable for both trapezoidal and sinusoidal motor control in page 1. 06-18-08 corrected internal dead time on front pag e to 530ns instead of 540ns.

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